1. Field of the Invention
The present invention relates to a memory and particularly to an FIFO (first-in first-out) type memory.
2. Description of the Background Art
FIG. 5 is a circuit diagram of the construction of a conventional FIFO type memory 200. The memory 200 is, for example, used for digital transmissions or communication units.
The memory 200 has a two-port type RAM 101 that can perform writing and reading independently, a read address generator 202 for generating a 3-bit read address 21, and a write address generator 203 for generating a 3-bit write address 22.
In synchronization with the fall of a signal provided to a clock end CLR, the RAM 101 outputs, as a data Dout less than 3:0 greater than , the data stored in the address specified by the read address 21 inputted to a read address terminal RA less than 2:0 greater than , from a data output end DO less than 3:0 greater than  (read operation). Also, in synchronization with the rise of a signal provided to a clock end CLW, the RAM 101 stores a data Din less than 3:0 greater than  inputted to a data input end DI less than 3:0 greater than  at the address specified by the write address 22 inputted to a write address terminal WA less than 2:0 greater than  (write operation). Here, a clock CLK is being provided to both the read clock end CLR and the write clock end CLW.
The memory 200 so constructed performs the FIFO type data input-output operation such that the write address 22 always takes the address value, which the read address 21 takes before a fixed period of time. FIGS. 6 and 7 are circuit diagrams showing the constructions of a read address generator 202 and a write address generator 203, respectively.
Referring to FIG. 6, when a reset signal RST is in the state of xe2x80x9cLxe2x80x9d, the outputs of gates 40, 46 and 47 are always in xe2x80x9cHxe2x80x9d, xe2x80x9cLxe2x80x9d and xe2x80x9cLxe2x80x9d, respectively. Therefore, regardless of the number of times a clock CLK rises, Q-outputs of D-type flip-flops 43, 48 and 49 remain in xe2x80x9cHxe2x80x9d, xe2x80x9cLxe2x80x9d and xe2x80x9cLxe2x80x9d, respectively. Thereafter, when the reset signal RST becomes xe2x80x9cHxe2x80x9d, the Q-output of the D-type flip-flop 43 inverted by an inverter 41 becomes the D-input of the D-type flip-flop 43 and, each time the clock CLK rises, the Q-output of the D-type flip-flop 43 alternates between xe2x80x9cLxe2x80x9d and xe2x80x9cHxe2x80x9d. Consequently, the sum-outputs S of half adders 44 and 45 provide D-inputs of the D-type flip-flops 48 and 49, respectively. Since the D-inputs of the D-type flip-flops 48 and 49 become add-inputs A of the half adders 45 and 44, respectively, the Q-outputs of the D-type flip-flops 49 and 48 divide the clock CLK by two and four, respectively. Hence, let xe2x80x9cHxe2x80x9d be xe2x80x9c1xe2x80x9d and xe2x80x9cLxe2x80x9d be xe2x80x9c0xe2x80x9d, a read address 21 is produced that cycles as follows: 001, 010, 011, . . . , 111, 000, 001, . . . , can be generated by locating the Q-outputs of the D-type flip-flops 48, 49, 43 in this order, i.e., in the order of descending bit position.
Referring to FIG. 7, when a reset signal RST is in the state of xe2x80x9cLxe2x80x9d, the outputs of gates 42, 46 and 47 are always in xe2x80x9cLxe2x80x9d, xe2x80x9cLxe2x80x9d and xe2x80x9cLxe2x80x9d, respectively. Accordingly, in the same manner as in the address generator 202, a write address 22 is produced that cycles as follows: 000, 001, 010, . . . , 110, 111, 000, . . . , can be generated.
As stated earlier, in the conventional memory 200 there are provided a pair of very similar circuits and merely by a difference between the gates 40 and 42, the write address 22 generated by write address generator 203 is effectively delayed from the read address 21 by a period of one cycle of a clock CLK, thereby transmitting data with a delay of cycles, i.e., (the total number of addressesxe2x88x921) (herein, 23xe2x88x921=7). Unfortunately, this increases the scale of a circuit needed in address generation.
According to a first aspect of the present invention, a FIFO type memory comprises: a read address generator for generating a read address in synchronization with a clock signal; an address delayor that generates a write address by delaying the read address in synchronization with the clock signal; and a storage element that inputs data to an address specified by the read address and outputs data from an address specified by the write address, in synchronization with the clock signal.
In the semiconductor memory of the first aspect, since a write address is generated by delaying a read address, the circuit scale required for generating write addresses can be reduced to realize the operation of the FIFO type.
According to a second aspect of the present invention, the FIFO type memory of the first aspect is characterized in that the read address is generated cyclically.
Preferably, the amount of delay of an address delayer is set to a period of a clock signal. As a result, a delay of data, i.e., storage, can be achieved by a period of a clock cycle being the longest in the FIFO operation, i.e., which is obtained by subtracting a one from the number of read address patterns to be generated cyclically.
According to a third aspect of the present invention, the FIFO type memory of the second aspect is characterized in that the address delayer has D-type flip-flops whose number is equal to the number of bits constituting the read address; and that each bit of the read address is provided to the data input ends of the D-type flip-flops.
Preferably, a clock signal is provided in common to each clock input end of the D-type flip-flops. This enables to obtain the respective bits constituting a write address from the data output ends of the D-type flip-flops.
Thus, an object of the present invention is to provide an FIFO type memory on a small scale circuit.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.